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IC-DC 2-channel buck/boost dc/dc converter rev a3, page 1/ 19 features ? wide input voltage range of +4 to +36 v ? reverse polarity protection up to -36 v with autarky function ? universal buck/boost converter with high ef?ciency ? two back-end, adjustable linear regulators (1.5 v to 5.5 v) with a total of up to 300 ma of output current and a separate output voltage monitor ? low residual ripple with small capacitors in the f range ? separate enable inputs for the linear regulators ? two switched linear regulator outputs ? integrated switching transistors and ?yback diodes ? converter cut-off current can be set by an external resistor ? integrated 3 mhz oscillator with no external components ? active noise spectrum reduction ? error messaging with overtemperature, overvoltage, and undervoltage at the current-limited open-collector output ? wide temperature range of -40 c to 125 c ? protective circuitry against esd ? space saving 24-pin qfn package applications ? dual voltage supply by buck/boost converters with adjustable, back-end linear regulators ? power management for laser, encoder, and automotive applications packages qfn24 4 mm x 4 mm (rohs compliant) block diagram copyright ? 2011 ic-haus http://www.ichaus.com v o l t a g e e n a b l e r 2 r 3 r 4 o u t p u t s w i t c h 2 5 v / 3 . 3 v / r 1 : r 2 v c c 1 : v c c 2 : s w i t c h 1 v o l t a g e m o n i t o r p r o t e c t . s u p p l y t h e r m a l s h u t d o w n b u c k s u p p l y s u p p l y l i n . - r e g . 1 l i n . - r e g . 2 c o n t r o l m o n i t o r i n g r e f e r e n c e b i a s b o o s t s w i t c h i n g r e g u l a t o r 3 . 3 v / 2 . 5 v / r 3 : r 4 r 1 o s c i l l a t o r i c - d c e r r o r d e t e c t . a u t a r k y d e t e c t . r e v e r s e i n t e r n a l c o n f i g u r a t i o n 2 0 k r r e f 1 f c v b c v b r 1 0 f 2 1 2 l v b h 2 2 h c v h 1 3 . 3 f 3 . 3 f c v h 1 f c v c c 2 c v c c 1 1 f 3 . 3 f c v h 2 & 1 2 1 v c c 1 r r e f v c c 1 , v c c 2 t e s t v 1 o k v 2 o k v c c 2 p o e 2 t o k v b r o k v h 1 v c c 1 v c c 2 g n d v b r v b l v h l v h g n d a v b c f g 1 c f g 2 e n v 1 e n v 2 n a u t 4 . . . 3 6 v 1 . 5 . . . 5 . 5 v 1 . 5 . . . 5 . 5 v v h 2 p o e 1 r r e f 2 0 k c v b 1 f 1 0 f c v b r l v b h 2 2 h c v c c 2 1 f 1 f c v c c 1 c v h 2 3 . 3 f 3 . 3 f c v h 1 c v h 3 . 3 f & p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 2/ 19 description IC-DC is a monolithic switching converter with two back-end linear regulators. the output voltages of the two linear regulators can be individually pin- con?gured within a range of 1.5 to 5.5 v. the switch- ing converter supplies up to 300 ma which can be drawn from the two linear regulators in the ratio re- quired. the intermediate voltages of the two on-chip linear regulators are adjusted to minimize their drop-out voltages. these are approximately 400 mv above the set linear regulator output voltages. the high ef?ciency of the buck/boost converter for an input voltage range of +4 v to +36 v makes IC-DC suitable for industrial applications. using very few ex- ternal components, a dc/dc power pack can be cre- ated with a stabilized supply voltage and minimum power dissipation. IC-DC is ideal for sensor applications thanks to its minimal power loss, few components, and stabilized supply. switching transistors, ?yback diodes, and an oscillator are integrated in the device so that the only external elements needed are an inductor, the back- up capacitors, and a reference resistor. the back-end linear regulators have a very low resid- ual ripple with comparatively small ?lter capacitors in the single-digit f range. by using two independent regulators voltages can be decoupled from sensitive analog circuits and driver devices, for example. the chip temperature, input voltage, and integrated reverse polarity protection are monitored and errors signaled by current-limited open-collector outputs. with overtemperature the switching converter is dis- abled to reduce the chips power dissipation. the linear regulator output voltages are monitored and once having reached the steady state they are also switched to outputs poe1 and poe2. the out- put voltages of the two linear regulators vcc1 and vcc2 can be switched on and off by two separate inputs. the devices standby function can be activated to minimize the current consumption. p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 3/ 19 contents packages 4 package dimensions . . . . . . . . . . . 5 absolute maximum ratings 6 thermal data 6 electrical characteristics 7 description of functions 11 charge/discharge phase . . . . . . . . . . . . 11 intermittent ?ow / continuous ?ow . . . . . . . 12 startup behavior . . . . . . . . . . . . . . . . 12 standby . . . . . . . . . . . . . . . . . . . . . 12 linear regulators vcc1 and vcc2 13 switched output voltages . . . . . . . . . . . 13 voltage monitor self-test . . . . . . . . . . . . 13 current carrying capacity . . . . . . . . . . . 13 reverse polarity protection 14 error evaluation 15 supply voltage monitor . . . . . . . . . . . . . 15 output voltage monitor . . . . . . . . . . . . . 15 output voltage monitor self-test . . . . . . . . 15 temperature monitor . . . . . . . . . . . . . . 15 autarky function 15 description of the application 16 selecting the coil . . . . . . . . . . . . . . . . 16 selecting the capacitors . . . . . . . . . . . . 16 printed circuit board layout . . . . . . . . . . 16 example application 17 design review: notes on chip functions 17 p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 4/ 19 packages pin configuration qfn24-4x4 (4 mm x 4 mm) pin functions no. name function 1 rref reference resistor 2 gnda analog ground 3 cfg1 vcc1 con?guration 3.3/5.0 v or 1.5 v to 5.5 v with ext. r divider 4 cfg2 vcc2 con?guration2.5/3.3 v or 1.5 v to 5.5 v with ext. r divider 5 test test input 6 poe2 power output enable vcc2 voltage 7 v2ok error output vcc2 voltage 8 vcc2 1.5 v to 5.5 v lin. regulator output 2 9 vh2 intermediate voltage 2 for vcc2 regulator 10 vh1 intermediate voltage 1 for vcc1 regulator 11 vcc1 1.5 v to 5.5 v lin. regulator output 1 12 v1ok error output vcc1 voltage 13 poe1 power output enable vcc1 voltage 14 vh intermediate voltage 15 vhl inductor terminal vh 16 gnd power ground 17 vbl inductor terminal vb 18 vbr reverse protected supply voltage 19 vb +4 v to +36 v supply voltage 20 env1 vcc1 linear regulator activation 21 env2 vcc2 linear regulator activation 22 vbrok error output supply voltage 23 tok error output overtemperature 24 naut error output autarky tp thermal pad the thermal pad on the underside of the package should be appropriately connected to gnd for better heat dissipation (ground plane). gnda should also be directly connected to neutral point gnd. ground loops should be avoided. only the pin 1 mark on the front or reverse is determinative for package orientation ( dc and code are subject to change). p r e l i m i n a r y p r e l i m i n a r y yyww... ... dc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 5/ 19 package dimensions all dimensions given in mm. p r e l i m i n a r y p r e l i m i n a r y 4 4 0.90 side 0.25 0.50 2.45 2.45 0.40 bottom 2.49 3.80 2.49 3.80 r0.15 0.50 0.30 0.70 recommended pcb-footprint dra_qfn24-1_pack_1, 10:1 top
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 6/ 19 absolute maximum ratings maximum ratings do not constitute permissible operating conditions; functionality is not guaranteed. exceeding the maximum ratings can damage the device. item symbol parameter conditions unit no. min. max. g001 v() voltage at vb -40 42 v g002 v() voltage at vbr, vbl, env1, env2 -0.3 42 v g003 v() voltage at vhl, vh, vbrok, naut, tok, test -0.3 8.4 v g004 v() voltage at vh1, vh2 -0.3 6.4 v g005 v() voltage at vcc1, vcc2, v1ok, v2ok, cfg1, cfg2, poe1, poe2, rref, gnda -0.3 5.6 v g006 i(vb) current in vb -50 800 ma g007 i(vbr) current in vbr -50 800 ma g008 i(vbl) current in vbl -800 50 ma g009 i(vhl) current in vhl -50 800 ma g010 i() current in vh, vh1, vh2, vcc1, vcc2 -500 20 ma g011 i() current in cfg1, cfg2, env1, env2, v1ok, v2ok, vbrok, naut, tok, poe1, poe2, rref, test, gnda -20 20 ma g012 vd() esd susceptibility at all pins hbm, 100 pf discharged through 1.5 k
2 kv g013 tj chip-temperature -40 150 c g014 ts storage temperature range -40 150 c thermal data operating conditions: vb = +4 v to +36 v item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature range -40 125 c t02 rthja thermal resistance chip to ambient qfn24 surface mounted, thermal-pad soldered to approx. 2 cm2 copper area on the pcb 30 40 k/w all voltages are referenced to ground (pin gnd: power ground) unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative. p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 7/ 19 electrical characteristics operating conditions: vb = +4 v to +36 v, rref = 20 k
1 %, tj = -40c to +125c, reference is gnd (gnda = gnd), unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. total device 001 vb permissible supply voltage 4 36 v 002 i() supply current in vb env1 = lo, env2 = lo, standby 20 100 200 a 003 i() supply current in vb only one linear regulator active, no load current, no external voltage divider vb = 24 v 1.5 3 8 ma vb = 12 v 2.5 5.5 15 ma vb = 4 v 10 22 50 ma 004 i() supply current in vb both linear regulators active, no load current, no external voltage divider vb = 24 v 2 4 10 ma vb = 12 v 3 7 20 ma vb = 4 v 12 25 60 ma 007 ipd() pull-down current in env1, env2 v() = 2...36 v 15 150 a 009 vt()hi input threshold voltage hi at env1, env2 2 v 010 vt()lo input threshold voltage lo at env1, env2 0.8 v 011 vt()hys input hysteresis at env1, env2 vt()hys = vt()hi vt()lo 100 200 400 mv 012 vc()lo clamp voltage lo at all pins with exception of vb versus gnd, i() = -10 ma -1.4 -0.3 v 013 vc()lo clamp voltage lo at vb versus gnd, i() = -2 ma -60 -42 v 014 vc()hi clamp voltage hi at vb vbr, vbl, env1, env2 versus gnd, i() = 2 ma 42 60 v 015 vc()hi clamp voltage hi at vbrok, naut, tok, test versus gnd, i() = 1 ma 9 18 v 016 vc()hi clamp voltage hi at vh versus gnd, i() = 5 ma 8.3 18 v 017 vc()hi clamp voltage hi at vh1, vh2 versus gnd, i() = 10 ma 6.2 18 v 018 vc()hi clamp voltage hi at vcc1, vcc2, poe1, poe2, cfg1, cfg2 versus gnd, i() = 10 ma 5.6 18 v 019 vc()hi clamp voltage hi at gnda, rref versus gnd, i() = 10 ma 2.5 18 v 020 vc()hi clamp voltage hi at v1ok, v2ok v1ok versus vcc1, v2ok versus vcc2, i() = 2 ma 0.3 1.4 v 021 vc()hi clamp voltage hi at vhl versus vh, i() = 10 ma 0.3 1.4 v reverse polarity protection vb, vbr and autarky detection naut 101 vs()hi saturation voltage hi at vbr vs(vbr)hi = vb v(vbr), i(vbr) = -100 ma 0.3 0.6 v 103 izu() maximum permissible current hi from vbr at startup v(vbr) = 0...3 v, vb increasing -5 0 ma 104 imax() maximum current from vbr v(vbr) = 2 v...vb 0.6 v -500 -250 -120 ma 105 imax() maximum current from vbr v(vbr) = 0 v -150 -10 ma 108 ir() leakage current from vb at autarky vbr > vb + 50 mv -0.5 0 ma 109 d(vb,vbr) voltage difference for autarky vbr versus vb; naut = lo 25 12.5 0 mv 110 ir,max() maximum current from vb vb < vbr < vb + 50 mv -10 -4 0 ma 111 ir() reverse current from vb -36v < vb < gnd -1 0 ma 112 vs()lo saturation voltage lo at naut i(naut) = 5 ma, naut = lo 0.4 v 113 isc()lo short-circuit current lo in naut v(naut) = 2...8 v, naut = lo 10 20 ma 114 ilk() leakage current in naut v(naut) = 0...8 v, naut = hi -10 10 a voltage monitoring vbr and error detection vbrok 201 vt1()hi lower turn-on threshold vbr vbr increasing, vbrok: lo ! open 3.75 3.95 v 202 vt1()lo lower turn-off threshold vbr vbr decreasing, vbrok: open ! lo 2.8 3.15 v p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 8/ 19 electrical characteristics operating conditions: vb = +4 v to +36 v, rref = 20 k
1 %, tj = -40c to +125c, reference is gnd (gnda = gnd), unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. 203 vt1()hys hysteresis vbr vt1()hys = vt1()hi vt1()lo 300 600 mv 204 vt2()hi overvoltage detection at vbr vbr increasing, vbrok: open ! lo 40.4 42 v 205 vt2()lo reset overvoltage detection at vbr vbr decreasing, vbrok: lo ! open 35 37.6 v 206 vt2()hys hysteresis vbr vt2()hys = vt2()hi vt2()lo 1 2.8 4 v 210 vs()lo saturation voltage lo at vbrok i(vbrok) = 5 ma, vbrok = lo 0.4 v 211 isc()lo short-circuit current lo in vbrok v(vbrok) = 2..8 v, vbrok = lo 50 ma 212 ilk() leakage current in vbrok v(vbrok) = 0..8 v, vbrok = hi -10 10 a 213 v(vbr) minimal supply voltage for vbrok function i(vbrok) = 5 ma, vbrok = lo, vs(vbrok)lo < 0.4 v 3.2 v switching regulator vh, vh1, vh2 305 v() voltage at vh lvbh = 22 h 20 %, ri(lvbh) < 1.1
, cvh = 1 f; vb 5 v, i(vh) = -50 ma, 7 7.75 8 v vb > 5 v, i(vh) = -100 ma, 7.25 7.75 8 v vb 12 v, i(vh) = -200 ma, 7.25 7.75 8 v vb 24 v, i(vh) = -300 ma 7.25 7.75 8 v 307 cvh required capacitor at vh tolerance 30 % 1 f 308 rivh permissible internal resistance of capacitor at vh 1
309 v() voltage at vh1 versus vcc1, cvh1 = 1 f, 300 400 600 mv vb 5 v, i(vh1) = -50 ma, vb > 5 v, i(vh1) = -100 ma, vb 12 v, i(vh1) = -200 ma, vb 24 v, i(vh1) = -300 ma 311 cvh1 required capacitor at vh1 tolerance 30 % 1 f 312 ricvh1 permissible internal resistance of capacitor at vh1 1
313 v() voltage at vh2 versus vcc2, cvh2 = 1 f, 300 400 600 mv vb 5v, i(vh2) = -50 ma, vb > 5 v, i(vh2) = -100 ma, vb 12 v, i(vh2) = -200 ma, vb 24 v, i(vh2) = -300 ma 315 cvh2 required capacitor at vh2 tolerance 30 % 1 f 316 ricvh2 permissible internal resistance of capacitor at vh2 1
330 vh ef?ciency of switching converter vh vb = 4 v, v(vh) > 7 v, vb = vbr, vh1 > vcc1 + 800 mv, vh2 > vcc2 + 800 mv 70 % 331 vh ef?ciency of switching converter vh vb = 6.5 v, v(vh) > 7 v, vb = vbr, vh1 > vcc1 + 800 mv, vh2 > vcc2 + 800 mv 80 % 332 vh1 ef?ciency of switching converter vh1 vb = 4 v, v(vh) > 8.1 v, vb = vbr, env1 = hi, env2 = lo 70 % 333 vh1 ef?ciency of switching converter vh1 80 % 334 vh2 ef?ciency of switching converter vh2 vb = 4 v, v(vh) > 8.1 v, vb = vbr, env1 = lo, env2 = hi 70 % 335 vh2 ef?ciency of switching converter vh2 vb = 6.5 v, v(vh) > 8.1 v, vb = vbr, env1 = lo, env2 = hi 80 % bias, oscillator and reference rref 401 v() voltage at rref resistor rref = 20 k
1 %, resistor rref versus gnda 1.18 1.24 1.3 v 402 r() permissible resistor at rref 1 % 19.6 34 k
403 isc() short-circuit current lo in rref v(rref) = 0 v -3 -0.5 ma p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 9/ 19 electrical characteristics operating conditions: vb = +4 v to +36 v, rref = 20 k
1 %, tj = -40c to +125c, reference is gnd (gnda = gnd), unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. 404 fos oscillator frequency resistor rref = 20 k
1 %, resistor rref versus gnda 2 7 mhz linear regulator vcc1 501 vcc1 nom,hi output voltage cfg1 = vcc1; 4.75 5 5.25 v vb < 5 v, i(vcc1) = -60...10 ma, vb 5 v, i(vcc1) = -100...10 ma, vb 6.5 v, i(vcc1) = -150...10 ma, vb 12 v, i(vcc1) = -200..10 ma, vb 24 v, i(vcc1) = -250...10 ma 502 vcc1 nom,lo output voltage cfg1 = gnda; 3.135 3.3 3.465 v vb < 5 v, i(vcc1) = -100...10 ma, vb 5 v, i(vcc1) = -150...10 ma, vb 6.5 v, i(vcc1) = -200...10 ma, vb 16 v, i(vcc1) = -300...10 ma, vb 24 v, i(vcc1) = -350...10 ma, 503 vr(cfg1) transmission ratio of external voltage divider r(vcc1/cfg1) / r(cfg1/gnda) v(vcc1) = (1 + r(vcc1/cfg1) / r(cfg1/gnda)) * v(rref), r(vcc1/cfg1) + r(cfg1/gnda) = 10 k
...50 k
1 %, v(vcc1) = 1.5...5.5 v 0.2 3.5 504 cvcc1 required capacitor at vcc1 versus gnda tolerance 30 % 1 f 505 ricvcc1 permissible internal resistance of capacitor at vcc1 1
506 vcc1,lir line regulation i(vcc1) = -100 ma, vb = 8...30 v -20 20 mv 507 vcc1,lor load regulation vb = 24 v, i(vcc1) = 0...200 ma -20 20 mv 508 vcc1rip output ripple i(vcc1) = -100ma 10 mvpp linear regulator vcc2 601 vcc2 nom,hi output voltage cfg2 = vcc2; 3.135 3.3 3.465 v vb < 5 v, i(vcc2) = -100...10 ma, vb 5 v, i(vcc2) = -150...10 ma, vb 6.5 v, i(vcc2) = -200...10 ma, vb 16 v, i(vcc2) = -300...10 ma, vb 24 v, i(vcc2) = -350...10 ma 602 vcc2 nom,lo output voltage cfg2 = gnda; 2.375 2.5 2.625 v vb < 5 v, i(vcc2) = -150...10 ma, vb 5 v, i(vcc2) = -200...10 ma, vb 6.5 v, i(vcc2) = -250...10 ma, vb 12 v, i(vcc2) = -300...10 ma, vb 24 v, i(vcc2) = -350...10 ma 603 vr(vcc2) transmission ratio of external voltage divider r(vcc2/cfg2) / r(cfg2/gnda) v(vcc2) = (1 + r(vcc2/cfg2) / r(cfg2/gnda)) * v(rref), r(vcc2/cfg2) + r(cfg2/gnda) = 10 k
...50 k
1 %, v(vcc2) = 1.5...5.5 v 0.2 3.5 604 cvcc2 required capacitor at vcc2 versus gnda tolerance 30 % 1 f 605 ricvcc2 permissible internal resistance of capacitor at vcc2 1
606 vcc2,lir line regulation i(vcc2) = -100 ma, vb = 8...30 v -20 20 mv 607 vcc2,lor load regulation vb = 24 v, i(vcc2) = 0...200 ma -20 20 mv 608 vcc2rip output ripple i(vcc2) = -100ma 10 mvpp p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 10/ 19 electrical characteristics operating conditions: vb = +4 v to +36 v, rref = 20 k
1 %, tj = -40c to +125c, reference is gnd (gnda = gnd), unless otherwise stated. item symbol parameter conditions unit no. min. typ. max. voltage monitoring v1ok, v2ok (x = 1, 2) 701 vtu()lo lower undervoltage threshold vccx for vxok = lo versus vccxnom 90 92 94 %vcc2 702 vtu()hi upper undervoltage threshold vccx for vxok = hi versus vccxnom 91 93 95 %vcc2 703 vto()lo lower overvoltage threshold vccx for vxok = hi versus vccxnom 105 107 109 %vcc2 704 vto()hi upper overvoltage threshold vccx for vxok = lo versus vccxnom 106 108 110 %vcc2 705 vt()hys hysteresis under-/overvoltage vccx versus vccxnom 0.25 1 1.5 %vcc2 706 vs()lo saturation voltage lo vxok = lo; i() = 4 ma, vccx 3 v 0.4 v i() = 1 ma, vccx < 3 v 0.4 v 707 vs()hi saturation voltage hi vs()hi = vccx v(), vxok = hi; i() = -4 ma, vcc2 3 v 0.4 v i() = -1 ma, vcc2 < 3 v 0.4 v 708 isc()lo short-circuit current lo v() = vccx, vxok = lo; vccx 3 v 6 80 ma vccx < 3 v 1 30 ma 709 isc()hi short-circuit current hi v() = 0 v, vxok = hi; vccx 3 v -100 -6 ma vccx < 3 v -30 -1 ma supply switches poe1, poe2 (x = 1, 2) 801 vs()hi saturation voltage hi vs()hi = vccx v(poex); v(vccx) 2.5 v, i(poex) = -10 ma, v1ok, v2ok = hi 0.2 v 802 vs()hi saturation voltage hi vs()hi = vccx v(poex); v(vccx) < 2.5 v; i(poex) = -5 ma, v1ok, v2ok = hi 0.2 v 803 isc()hi short-circuit current hi v(poex) = 0 v; v(vccx) 2.5 v, poex = hi, v1ok, v2ok = hi -40 -12 ma 804 isc()hi short-circuit current hi v(poex) = 0 v; v(vccx) < 2.5 v, poex = hi, v1ok, v2ok = hi -30 -6 ma thermal shutdown and error detection tok 901 toff thermal shutdown threshold 150 160 175 c 902 ton restart temperature 135 150 165 c 903 thys temperature hysteresis thys = toff ton 5 10 20 c 904 vs()lo saturation voltage lo i(tok) = 5 ma; tok = lo 0.4 v 905 isc()lo short-circuit current lo v(tok) = 2..8 v; tok = lo 10 20 ma 906 lk() leakage current v(tok) = 0..8 v; tok = hi -10 10 a test input test a01 vt()hi threshold voltage hi for com- parator test 0.64 0.7 v a02 vt()lo threshold voltage lo for com- parator test 0.54 0.6 v a03 vt()hys hysteresis at test vt() = vt(test)hi vt(test)lo 10 40 100 mv a05 ipd() pull-down current in test v() = 5.5 v 20 200 a a07 tsu(test) settling time at v1ok, v2ok v1ok, v2ok changing hi ! lo 10 20 30 s a08 tsu(test) settling time at v1ok, v2ok v1ok, v2ok changing of lo ! hi 2 4 8 s p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 11/ 19 description of functions dc/dc converter IC-DC generates two regulated volt- ages of vh1 and vh2 from voltage vbr. these presta- bilize the two linear regulators vcc1 and vcc2. a third voltage of vh, also regulated, is generated to drive these linear regulators. voltage supply vb may be either above or below the output voltages. figure 1 shoes the basic function principle of IC-DC. switches s1 to s6 and diode d1 have been implemented on the chip. the inductor, capacitors, and load resistors are external devices. figure 1: principle of operation of the converter another feature of IC-DC is that bias voltages vh1 and vh2 adjust themselves automatically to approximately 400 mv using the selected vcc1 or vcc2 voltage. this results in minimum power dissipation as only a low amount of voltage is lost through each of the linear regulators. charge/discharge phase during the charge phase switches s 1 and s 2 close with the internal clock. a linearly increasing current ?ows through coil lvbh. the energy from supply vbr is stored in the coils magnetic ?eld. switches s 1 and s 2 open for discharging. switch s 3 and one of the switches s 4 /s 5 /s 6 are closed. the cur- rent can continue to ?ow in the coil and is supplied to the relevant capacitor and relevant load. figure 2 de- scribes the resulting course of the current and voltage. the current rise and fall times depend on the inductor voltage. figure 2: converter current/voltage characteristics (vb = 4 v) p r e l i m i n a r y p r e l i m i n a r y r v h 2 c v h 2 r v h r v h 1 c v h c v h 1 s 2 s 4 s 5 s 6 s 3 d 1 v h v h 1 v h 2 v h l v b r v b l v b l v b h s 1 l v b h s 1 s 3 d 1 s 2 s 4 s 5 s 6 c v h c v h 1 c v h 2 r v h r v h 1 r v h 2 dual 3.3v/5v boost/buck smps, 05.05.2008 11:51:33 v(vhl) 8.887ms 8.888ms 8.889ms 8.89ms time (linear) [plot 0] 0 2v 4v 6v 8v v(vbl) -1v 0 1v 2v 3v 4v i(lvbh) 0 100ma 200ma 300ma 400ma
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 12/ 19 intermittent ?ow / continuous ?ow if the inductor is recharged in the next cycle before the coil current has run free, there is no gap in the current. this continuous ?ow occurs when the supply voltage is low or the load current high. if the charge and discharge processes are concluded within one clock cycle and the coil current drops to zero each time, intermittent ?ow prevails. this is the case when the supply voltage is suf?ciently high or the load current suf?ciently low. when no more current ?ows through the coil, after ?y- back in intermittent operation both ends of the inductor are switched to ground. this prevents the oscillations in no-load operation that are typical of many converters (rlc resonating circuit). this helps to achieve better emc behavior. startup behavior during startup and with low supply voltages the coils maximum cut-off current is reduced (soft start) until the nominal voltage is reached at vh. figure 3 shows the startup behavior for vh, vcc1 (5 v), and vcc2 (3.3 v) with the voltage monitor outputs v1ok and v2ok. as three output voltages are generated with this switching converter topology using just one single in- ductor, the sequence must allow that all three con- verter outputs are respectively supplied with the re- quired current. the core of the converter consists of three independent converters. each converter has its own regulated cut-off and restart current and its own voltage monitor. during the startup phase the vh con- verter ramps up until a voltage of approximately 7 v is obtained. here, the cut-off current is initially limited to lower values so that a soft start with a low startup cur- rent ripple is achieved. when a high enough vh voltage is available, the vh1 and vh2 converters are also switched on and the volt- ages rise to their nominal values. once in a steady state, the individual converters are cyclically supplied by the inductor with precisely the amount of current that is required at that moment. the maximum load current can thus be drawn from each of the voltages vh, vh1, vh2, vcc1, or vcc2. standby the converters can be individually activated by pins env1 and env2. if neither of the two inputs are trig- gered, the device is in standby mode and the current consumption is reduced to a minimum. as soon as one of the two inputs becomes active, the vh voltage is also available. figure 3: startup principle for voltages vh, vcc1, vcc2, v1ok, and v2ok dual 3.3v/5v boost/buck smps, 08.05.2008 08:51:13 v(vh) v(vcc1) v(vcc2) 500us 550us 600us time (linear) [plot 0] 0 2v 4v 6v 8v v(v1ok) v(v2ok) 0 1v 2v 3v 4v 5v i(lvbh) 0 200ma 400ma 600ma p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 13/ 19 linear regulators vcc1 and vcc2 to achieve as low an interference voltage as possible, even with small ?lter capacitors c vh1 and c vh2 , an in- dependent linear regulator is connected after each of the intermediate voltages vh1 und vh2. output voltages vcc1 and vcc2 can each be ad- justed using a voltage divider at cfg1 and cfg2 within a range of 1.5 to 5.5 v 5 % and according to equations 1 and 2 . v vcc1 = v ( rref ) (1 + r 1 r 2 ) (1) and v vcc2 = v ( rref ) (1 + r 3 r 4 ) (2) nb: r 1 + r 2 bzw. r 3 + r 4 = 10 k
bis 50 k
inputs cfg1 and cfg2 can also be directly connected to the relevant output voltage vccx or gnda. the re- sulting voltages are given in tables 4 and 5 . vcc1 output voltage potential at cfg1 vcc1 gnda 3.3 v vcc1 5.0 v voltage divider 1.5 v to 5.5 v table 4: vcc1 settings vcc2 output voltage potential at cfg2 vcc2 gnda 2.5 v vcc2 3.3 v voltage divider 1.5 v to 5.5 v table 5: vcc2 settings the regulators have been compensated internally so that they are stable in no-load operation without an ex- ternal capacitor. stability across the entire load range is guaranteed by the minimum capacitances for c vcc1 and c vcc2 given in the electrical characteristics. the outputs are current limited to protect them against de- struction in the event of a short circuit. the two linear regulators can be switched on and off independently by inputs env1 and env2. if both reg- ulators are deactivated, IC-DC is in standby mode (see description of functions/standby). switched output voltages the two pins poe1 and poe2 are triggered by monitor outputs v1ok and v2ok and provide voltages drawn from vcc1 or vcc2. this enables the supply of spe- ci?c circuitry in a component group (e.g. eeproms) to be switched on only after vcc1 or vcc2 have reached their steady state. voltage monitor self-test using pin test the voltage monitoring comparators at v1ok and v2ok can be tested during ongoing opera- tion. the undervoltage and overvoltage thresholds of v1ok and v2ok are checked in turn with each test. for this purpose, pin test is increased to above the threshold voltage by an external driver. correct func- tioning is signaled by low signals at pins v1ok and v2ok. the function of the connected poe1 and poe2 outputs remains unaffected. current carrying capacity IC-DCs current carrying capacity depends on set out- put voltage vccx and input voltage vb. figure 4 shows the current carrying capacity dependent on the input voltage for various output voltages, measured on the IC-DC eval dc1d evaluation board. the in- ternal reverse polarity protective circuit was bridged (vb = vbr) to increase the current carrying capacity. figure 4: current carrying capacity for various out- put voltages dependent on vb (vb = vbr) 0,0 5,0 10,0 15,0 20,0 25,0 30,0 35,0 40,0 0,000 0,050 0,100 0,150 0,200 0,250 0,300 0,350 0,400 0,450 0,500 vh (>7.2v) 5v vccx 3,3v vccx 2,5v vccx 1,5v vccx input voltage vb [v] l o a d c u r r e n t [ m a ] p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 14/ 19 reverse polarity protection a protective switch inserted between supply vb and pin vbr protects the entire system against reverse po- larity. this can also be used to implement an autarky function (see autarky function). by connecting vb to vbr the reverse polarity protection circuit can be bridged to improve the current carrying capacity and the overall ef?ciency, especially if low supply voltages are used (figure 5 ). figure 5: protection against reverse polarity bridges vb to vbr the reverse polarity protection switch is current lim- ited to the maximum mean current consumption of the system (electrical characteristics 104). a capacitor (cvbr) must be connected to pin vbr if higher coil cut-off currents are to be supplied. this capacitor should have a value of at least 1 f at a supply voltage of vb = 24 v (figure 6 ). with very small supply voltages the value must be greater in or- der to cater for the higher power consumption during startup. the voltage at vbr must no longer drop below the lower shutdown threshold (electrical characteris- tics 202) to ensure safe converter startup. a capacitor of approx. 10 f should thus be selected for cvbr at a supply voltage of vb = 4 v (figure 7 ). figure 6: protection against reverse polarity active, cvbr for vb = 24 v figure 7: protection against reverse polarity active, cvbr for vb = 4 v it is possible to use the protective switch at pin vbr to provide further circuitry with protection against re- verse polarity (figure 9 , page 17 ). here, it must noted that the current carrying capacity of the reverse polar- ity protection (vbr) is limited on startup. as the device powers itself from vbr, the load at vbr must not be too high as otherwise converter operation cannot be initiated. the current carrying capacity on startup can be approximately described by equation 3 : i ( vbr ) = v ( vb ) 1 ma v (3) e n a b l e r 2 r 3 r 4 o u t p u t s w i t c h 2 p r o t e c t . s u p p l y v c c 2 : s w i t c h 1 v o l t a g e m o n i t o r l i n . - r e g . 2 c o n t r o l t h e r m a l s h u t d o w n b u c k s u p p l y s u p p l y l i n . - r e g . 1 m o n i t o r i n g r e f e r e n c e b i a s b o o s t s w i t c h i n g r e g u l a t o r 3 . 3 v / 2 . 5 v / r 3 : r 4 r 1 o s c i l l a t o r i c - d c e r r o r d e t e c t . a u t a r k y d e t e c t . r e v e r s e i n t e r n a l c o n f i g u r a t i o n v o l t a g e 2 5 v / 3 . 3 v / r 1 : r 2 v c c 1 : 1 2 2 h l v b h c v h 2 c v h 1 3 . 3 f 3 . 3 f c v h 1 f c v c c 2 c v c c 1 1 f 3 . 3 f 2 1 1 1 f c v b & 2 2 0 k r r e f r r e f v c c 1 , v c c 2 t e s t v 1 o k v 2 o k v c c 2 p o e 2 t o k v b r o k v h 1 v c c 1 v c c 2 g n d v b r v b l v h l v h g n d a v b c f g 1 c f g 2 e n v 1 e n v 2 n a u t 4 . . . 3 6 v 1 . 5 . . . 5 . 5 v 1 . 5 . . . 5 . 5 v v h 2 p o e 1 v c c 1 l v b h 2 2 h c v c c 2 1 f 1 f c v c c 1 c v h 2 3 . 3 f 3 . 3 f c v h 1 c v h 3 . 3 f c v b 1 f r r e f 2 0 k & v o l t a g e e n a b l e r 2 r 3 r 4 o u t p u t s w i t c h 2 5 v / 3 . 3 v / r 1 : r 2 v c c 1 : v c c 2 : s w i t c h 1 v o l t a g e m o n i t o r p r o t e c t . s u p p l y t h e r m a l s h u t d o w n b u c k s u p p l y s u p p l y l i n . - r e g . 1 l i n . - r e g . 2 c o n t r o l m o n i t o r i n g r e f e r e n c e b i a s b o o s t s w i t c h i n g r e g u l a t o r 3 . 3 v / 2 . 5 v / r 3 : r 4 r 1 o s c i l l a t o r i c - d c e r r o r d e t e c t . a u t a r k y d e t e c t . r e v e r s e i n t e r n a l c o n f i g u r a t i o n 2 0 k r r e f 1 2 2 h l v b h c v b r 1 f 1 f c v b c v h 1 3 . 3 f 3 . 3 f c v h 1 f c v c c 2 c v c c 1 1 f 3 . 3 f c v h 2 2 2 1 & 2 r r e f v c c 1 , v c c 2 t e s t v 1 o k v 2 o k v c c 2 p o e 2 t o k v b r o k v h 1 v c c 1 v c c 2 g n d 2 4 v 1 v b r v b l v h l v h g n d a v b c f g 1 c f g 2 e n v 1 e n v 2 n a u t 1 . 5 . . . 5 . 5 v 1 . 5 . . . 5 . 5 v v h 2 p o e 1 v c c 1 l v b h 2 2 h r r e f 2 0 k c v c c 2 1 f 1 f c v c c 1 c v h 2 3 . 3 f 3 . 3 f c v h 1 c v h 3 . 3 f c v b 1 f 1 f c v b r & l i n . - r e g . 2 c o n t r o l m o n i t o r i n g r e f e r e n c e b i a s b o o s t s w i t c h i n g r e g u l a t o r 3 . 3 v / 2 . 5 v / r 3 : r 4 r 1 o s c i l l a t o r i c - d c e r r o r d e t e c t . a u t a r k y d e t e c t . r e v e r s e i n t e r n a l c o n f i g u r a t i o n v o l t a g e e n a b l e r 2 r 3 r 4 o u t p u t s w i t c h 2 5 v / 3 . 3 v / r 1 : r 2 v c c 1 : v c c 2 : s w i t c h 1 v o l t a g e m o n i t o r p r o t e c t . s u p p l y t h e r m a l s h u t d o w n b u c k s u p p l y s u p p l y l i n . - r e g . 1 & 1 2 1 c v h 2 3 . 3 f 3 . 3 f c v h 1 c v h 3 . 3 f c v c c 2 1 f 1 f c v c c 1 2 2 1 l v b h 2 2 h c v b 1 f 1 0 f c v b r r r e f 2 0 k r r e f v c c 1 , v c c 2 t e s t v 1 o k v 2 o k v c c 2 p o e 2 t o k v b r o k v h 1 v c c 1 v c c 2 g n d 4 v v b r v b l v h l v h g n d a v b c f g 1 c f g 2 e n v 1 e n v 2 n a u t 1 . 5 . . . 5 . 5 v 1 . 5 . . . 5 . 5 v v h 2 p o e 1 v c c 1 & 1 f c v c c 2 c v c c 1 1 f 3 . 3 f c v h 2 c v h 1 3 . 3 f 3 . 3 f c v h 1 f c v b c v b r 1 0 f 2 2 h l v b h 2 0 k r r e f p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 15/ 19 error evaluation supply voltage monitor supply voltage vbr is monitored. if the normal volt- age range is overshot or undershot, this is signaled at open-drain pin vbrok. the bias current generated by an external reference resistor is also monitored and an error signaled at vbrok should the permissible range be exceeded. if an error has occurred, pin vbrok is switched to gnd. output voltage monitor the two linear regulator output voltages vcc1 and vcc2 are also monitored. if the overvoltage thresh- old is overshot or the undervoltage threshold under- shot (e.g. due to overload), a message is generated at the current-limited push-pull outputs v1ok and v2ok. voltage outputs poe1 and poe2 are shut down. output voltage monitor self-test using pin test the voltage monitoring comparators at v1ok and v2ok can be tested during ongoing opera- tion. the undervoltage and overvoltage thresholds of v1ok and v2ok are checked in turn with each test. for this purpose, pin test is increased to above the threshold voltage by an external driver. correct func- tioning is signaled by low signals at pins v1ok and v2ok. the function of the connected poe1 and poe2 outputs remains unaffected. temperature monitor the internal chip temperature is monitored. if the monitor indicates overtemperature, all switches on the switching converter are shut down. these are auto- matically re-enabled when the chip temperature has dropped below the restart temperature. a message is signaled at open-drain pin tok for as long as the con- verter is shut down due to chip overtemperature. the protective switch (vb / vbr) has its own over temperature protection, which is also operative during standby mode. as error outputs vbrok and tok are current limited, an led can be directly connected up for visual mes- sage display. however, the additional power dissipa- tion this causes in the ic must be taken into account. by placing resistor r led in series with the led, this additional chip power loss can be reduced in the event of error. cmos or ttl-compatible logic inputs can be activated by pull-up resistors at vbrok and tok. autarky function by inserting a capacitor at vbr, an autarky function can be realized should the supply fail at vb. this au- tarky function guarantees the linear regulator output voltages for some time. if the voltage at vbr is greater than at vb (elec. char. no. 109), this is signaled by current-limited open-drain output naut. to ensure that vbr > vb should the supply voltage fail, it is recom- mended that a resistor be switched between vb and gnd in order to generate the required differential volt- age of d vbr, vb . with this capacitor acting as a buffer, the effect of cur- rent spikes feeding back into the supply voltage vb is also reduced. p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 16/ 19 description of the application selecting the coil the coil should be designed for a maximum cut-off current of 1 a. a small internal resistor in the coil re- duces loss and increases converter ef?ciency. at a low supply voltage this internal resistor can determine the maximum available output current. the emi caused by the coil should be taken into con- sideration. toroidal core coils have little noise radia- tion yet are expensive and dif?cult to install. bar core coils are reasonably priced and easier to use yet have a higher noise emittance. for modest emi require- ments inexpensive radio interference suppression coils of several tens of h are suitable . selecting the capacitors selecting back-up capacitors c vh , c vh1 and c vh2 is unproblematic. as the residual ripple of intermediate voltages vh1 and vh2 does not affect output volt- ages vcc1 and vcc2 thanks to the back-end linear regulators, a small capacitor is suf?cient without any speci?c demands being made of the internal resis- tor. a combination of electrolytic and ceramic capaci- tors (e.g. 3.3 f || 100 nf) is recommended. before us- ing tantalum capacitors, the user must verify whether these are suitable for the residual ac amplitude (resid- ual ripple) at pins vh1 and vh2. stability of the linear regulators across the entire load area is guaranteed if the values given in the electrical characteristics are selected for cvcc1 and cvcc2. the suppression of interference voltage is improved by using small capacitor series resistors. a combina- tion of tantalum and ceramic capacitors is also recom- mended in this case. if one of the two outputs remains open, this capacitor can be omitted. to avoid feedback of interference from supply voltage vb onto output voltages vcc1 and vcc2, blocking should be provided directly at pin vb. a combination of tantalum and ceramic capacitors (e.g. 1 f || 100 nf) is also recommended in this case. printed circuit board layout the gnd path from the switching converter and from each linear regulator should be strictly separated to avoid cross couplings. the neutral point of all gnd paths is the gnd connection at IC-DC. it is possible and not critical, however, to route gnd from supply vb and the base point of capacitors c vh , c vh1 and c vh2 together to the neutral point. the capacitors should be very close to their relevant pins, however. blocking capacitors for supply vb should be arranged as close as possible to pins vb and gnd. the capaci- tors for outputs vcc1 and vcc2 should be placed di- rectly at the load and not at the ic to also block inter- ferences which are coupled via the wiring to the load. the ground planes underneath the wiring of output voltages vcc1, vcc2, poe1, and poe2 should be kept separate from the ground planes of switching con- verters vh, vh1, and vh2. the ground planes must be connected up at a neutral point (see figure 8 ). the thermal pad should be connected to the pcb by an appropriate ground plane. the resulting power dis- sipation can be transferred to a different wiring layer, e.g. a ground plane, by vias directly underneath the ic. figure 8: example layout: evaluation board dc1d e.g.: siemens matsushita b78108-s1224-j (22 h/1 a, axial), tdk series nlc565050t-. . . (smd), toko series 10rf459-. . . (smd shielded) p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 17/ 19 example application figure 9: application with IC-DC, ic-pt, and ic-dl the application diagram in figure 9 shows an example circuit featuring the dc/dc converter IC-DC. the input voltage range is set to between 4.5 v and 32 v by line driver ic-dl. the output voltages of the two linear reg- ulators are each con?gured to 5 v. vcc2 supplies the optical 6-channel incremental scanner ic-lta/ic-pt and vcc1 the 5 v section of 24 v line driver ic-dl. this creates a separation in the supply voltage be- tween the sensing mechanism and the digital switching section of the circuitry. the status signals for overvoltage (vbrok) and overtemperature (tok) in IC-DC are connected to ic- dls error message input tner. this links the ic- dc error messages to ic-dls own undervoltage and overtemperature monitor. ic-dls open-drain error message output ner thus provides the error mes- sages for both ics. this example circuit makes use of IC-DCs integrated reverse polarity protection feature. the illustrated diodes zd1, zd2, d2 to d13 and resistor r3 form the basis for a protective circuit against overvoltage for all outputs. no speci?c designations are given for these components as these protective circuits are to be indi- vidually con?gured and dimensioned according to the application and requirement. i n d e x o u t p u t a n d i c - t l 8 5 i c - p t s e r i e s v b 1 v o l t a g e e n a b l e l i n . - r e g . 1 s u p p l y o u t p u t s w i t c h 2 5 v / 3 . 3 v / r 1 : r 2 v c c 1 : v c c 2 : 4 . 5 . . 3 2 v s e l e c t r e s o l u t i o n n b u v w p z s u p p l y t h e r m a l s h u t d o w n b u c k s u p p l y l i n . - r e g . 2 c o n t r o l m o n i t o r i n g r e f e r e n c e s e l 0 v v b 3 p b p r o t e c t . l e d p o w e r c o n t r o l o u t p u t c o m p a r a t i o n s i g n a l b i a s b o o s t s w i t c h i n g r e g u l a t o r 3 . 3 v / 2 . 5 v / r 3 : r 4 o s c i l l a t o r e r r o r d e t e c t . a u t a r k y d e t e c t . r e v e r s e i n t e r n a l c o n f i g u r a t i o n m o n i t o r c o m m u t a t i o n p a s w i t c h 1 v o l t a g e i c - d c n e r r _ d c i c - d l n a v b 2 i c - l t a p o w e r - o n r e s e t q u a d r a t u r e n z + - c 1 1 0 0 n f r r e f 2 0 k 1 0 0 n f c 5 1 0 f c v b r d 1 2 d 1 3 d 1 0 d 1 1 d 5 d 6 d 7 d 3 d 4 d 1 d 2 d 9 z d 1 4 7 r l e d z d 2 c 2 1 0 0 n f r 3 c v b 1 f 1 1 d 8 1 0 0 n f 1 0 0 n f c 3 & c 4 c v h 3 . 3 f c v c c 2 1 f 1 f c v c c 1 3 . 3 f c v h 1 & 2 c v h 2 3 . 3 f l v b h 2 2 h 2 2 e r r o r d e t e c t i o n u n d e r v o l t a g e & o v e r t e m p e r a t u r e m o d e 1 r 2 2 k r e r r a 6 a 3 a 5 v b r r 1 3 0 . 1 k 1 0 k g n d s e l v c c 2 v c c 1 n e r a 1 a 2 a 4 e 2 e 3 e 4 e 5 e 6 g n d 3 v c c n e r a 1 a 2 a 3 a 4 a 5 a 6 v b 1 v b 2 v b 3 d i f f g n d 4 g n d 2 g n d 1 v c c 1 v c c 2 v c c 1 n e r r _ d c n e r r _ d c v b v c c l e d p a n z p z n b p b n a v b r e n a t n e r e 1 r r e f v c c 1 , v c c 2 t e s t v 1 o k v 2 o k v c c 2 p o e 2 t o k v b r o k v h 1 g n d g n d w v t i p t i n u v b r v b l v h l v h g n d a v b c f g 1 c f g 2 e n v 1 e n v 2 n a u t v h 2 p o e 1 v c c 1 2 0 k r r e f 1 0 0 n f c 1 r l e d 4 7 z d 1 d 1 d 2 d 9 d 3 d 4 d 5 d 6 d 7 d 1 0 d 1 1 d 1 2 d 1 3 c 5 1 0 0 n f c v b r 1 0 f z d 2 1 0 0 n f c 2 d 8 r 3 1 f c v b & 1 0 0 n f c 4 c 3 1 0 0 n f 3 . 3 f c v h 2 & 1 f c v c c 2 c v c c 1 1 f c v h 1 3 . 3 f 3 . 3 f c v h 2 2 h l v b h 0 1 0 1 1 o v e r t e m p e r a t u r e u n d e r v o l t a g e & e r r o r d e t e c t i o n & m o d e 0 1 3 0 . 1 k r 1 r 2 1 0 k r e r r 2 k p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 18/ 19 design review: notes on chip functions IC-DC z nr. function, parameter/code description and application hints 1 vc(vb)lo clamp voltage lo at vb (elec. char. no. 013) can have a maximum of -40 v at low temperature. table 6: notes on chip functions regarding IC-DC chip release z ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. p r e l i m i n a r y p r e l i m i n a r y
IC-DC 2-channel buck/boost dc/dc converter rev a3, page 19/ 19 ordering information type package order designation IC-DC qfn24 4 mm x 4 mm IC-DC qfn24-4x4 evaluation board IC-DC eval dc1d for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners p r e l i m i n a r y p r e l i m i n a r y

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